GUC Releases AI / HPC / Network Platform on TSMC CoWoS Technology
Article from: Global Unichip Corp.
Global Unichip has successfully registered the AI / HPC / Networking CoWoS platform with a 7.2 Gbps HBM3 controller and third party SerDes PHY, GLink-2.5D and 112G-LR IPs.
Global Unichip Corp. (GUC) has successfully registered a CoWoS AI / HPC / Network platform with a 7.2Gbps HBM3 controller and third party SerDes PHY, GLink-2.5D and 112G-LR IPs. The main matrix of the platform contains the world’s first HBM3 controller and a PHY IP address with record performance of 7.2 Gbit / s. The platform meets the stringent signal and power (SI and PI) integrity requirements of the 112G-LR SerDes routed via TSMC CoWoS technologies. GUC’s GLink-2.5D interface enables high bandwidth, low latency, and low power interconnection of multiple chips on the CoWoS platform. The success of bandwidth exceeds memory bandwidth limits and unleashes new potential for artificial intelligence (AI), high performance computing (HPC) and multi-die networking solutions.
The platform represents true use cases of AI / HPC / network applications that require the high flexibility of SoC floor plans and HBM3 PHY / controller layouts on the main chip versus HBM3 memory on the interposer . GUC’s patent pending solution allows HBM3 bus routing between PHY and memory at any angle while maintaining the same width and signal space as in traditional straight HBM bus routing. It provides shorter routing, better signal integrity, higher speed, and lower power consumption than traditional HBM zig-zag bus routing. Our products can support up to 10 HBM3 memories connected to two SoC chips using division PHY technology. GUC’s patent pending solution splits the central HBM3 memory bus into PHYs, located on two SoC chips to allow full use of HBM3 in SoC memory use cases: HBM3 2: 6 or 2:10.
GUC’s design for CoWoS and interposer supports 112G-LR SerDes signaling by adopting the internal interposer design flow and the latest TSMC CoWoS technology. To represent typical AI / HPC / network chip conditions, multiple instances of IP HBM3, 112G-LR SerDes and GLink-2.5D have been integrated into this large, high power CoWoS platform. GUC implemented a high coverage DFT solution for final production and wafer level testing. The DFT solution takes advantage of the redundancy and repair of the HBM3 and GLink-2.5D channels to maximize CoWoS throughput.
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“We are proud to be the first company in the world to create a full-scale 7.2 Gbps HBM3 controller and IP PHY. GUC has once again demonstrated its leadership in the industry by offering a complete solution for advanced packaging technology, ”said Dr. Ken Chen, President of GUC. “We have supplemented our HBM2E PHY / Controller, GLink-2.5D and GLink-3D IP portfolio with HBM3. Together with CoWoS, InFO_oS, 3DIC design expertise, packaging design, electrical and thermal simulations, DFT and production testing, we provide cutting edge solutions to our customers and help them achieve even more success in their products and activities.
“We integrated multiple instances of HBM3, 112G-LR SerDes and GLink-2.5D IP and very complex failover logic into a 280mm2, 400W chip and assembled multiple HBM3 chips and memories on a CoWoS platform. It validates our large-scale IPs under AI / HPC / network chip conditions and brings the great confidence of the robust operation of our IPs to large-scale products, ”said Igor Elkanovich, CTO of GUC. “We used our expertise in designing 112 Gbps multichannel packages with a silicon-correlated high-speed interposer design flow to validate 112 Gbps on the latest CoWoS solution. “